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Add tests for ECP5 architecture

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SergeyDegtyar 2019-09-03 11:53:37 +03:00
parent 7e8f7f4c59
commit 11f330ed22
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21
tests/ecp5/memory.v Normal file
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module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule