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ecp5: Initial arith_map implementation

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-13 15:46:12 +02:00
parent c2d7be140a
commit 11c916840d
3 changed files with 80 additions and 6 deletions
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1
techlibs/ecp5/Makefile.inc
View file

@ -5,3 +5,4 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))

78
techlibs/ecp5/arith_map.v Normal file
View file

@ -0,0 +1,78 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018 David Shah <dave@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
function integer round_up2;
input integer N;
begin
round_up2 = ((N / 2) + 1) * 2;
end
endfunction
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
wire [Y_WIDTH2-1:0] AA = A_buf;
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH2-1:0] C = {CO, CI};
wire [Y_WIDTH2-1:0] FCO;
genvar i;
generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
CCU2C #(
.INIT0(16'b0110011010101010),
.INIT1(16'b0110011010101010),
.INJECT1_0(1'b0),
.INJECT1_1(1'b0)
) ccu2c_i (
.CIN(C[i]),
.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
.S0(F0), .S1(F1),
.COUT(FCO[i])
);
assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
if (i < Y_WIDTH)
assign CO[i+1] = FCO[i];
end endgenerate
assign X = AA ^ BB;
endmodule

7
techlibs/ecp5/synth_ecp5.cc
View file

@ -236,15 +236,10 @@ struct SynthEcp5Pass : public ScriptPass
run("opt -fast -mux_undef -undriven -fine"); run("opt -fast -mux_undef -undriven -fine");
run("memory_map"); run("memory_map");
run("opt -undriven -fine"); run("opt -undriven -fine");
//TODO if (noccu2)
#if 0
if (nocarry)
run("techmap"); run("techmap");
else else
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
#else
run("techmap");
#endif
if (retime || help_mode) if (retime || help_mode)
run("abc -dff", "(only if -retime)"); run("abc -dff", "(only if -retime)");
} }