diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index f2cb5d9bc..e401cd718 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -510,7 +510,7 @@ struct AigerWriter } } - void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode) + void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode, bool ys_version) { int aig_obc = aig_o + aig_b + aig_c; int aig_obcj = aig_obc + aig_j; @@ -663,7 +663,8 @@ struct AigerWriter } } - f << stringf("c\nGenerated by %s\n", yosys_version_str); + if (ys_version) + f << stringf("c\nGenerated by %s\n", yosys_version_str); } void write_map(std::ostream &f, bool verbose_map, bool no_startoffset) @@ -919,6 +920,9 @@ struct AigerBackend : public Backend { log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n"); log(" AIGER file happy.\n"); log("\n"); + log(" -no_version\n"); + log(" don't write Yosys version\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { @@ -932,6 +936,7 @@ struct AigerBackend : public Backend { bool bmode = false; bool lmode = false; bool no_startoffset = false; + bool ys_version = true; std::string map_filename; std::string yw_map_filename; @@ -989,6 +994,10 @@ struct AigerBackend : public Backend { lmode = true; continue; } + if (args[argidx] == "-no_version") { + ys_version = false; + continue; + } break; } extra_args(f, filename, args, argidx, !ascii_mode); @@ -1010,7 +1019,7 @@ struct AigerBackend : public Backend { log_error("Found unmapped memories in module %s: unmapped memories are not supported in AIGER backend!\n", log_id(top_module)); AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode); - writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode); + writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode, ys_version); if (!map_filename.empty()) { rewrite_filename(filename); diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index baf504ba2..38761a9d9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -464,7 +464,7 @@ struct XAigerWriter } } - void write_aiger(std::ostream &f, bool ascii_mode) + void write_aiger(std::ostream &f, bool ascii_mode, bool ys_version) { int aig_obc = aig_o; int aig_obcj = aig_obc; @@ -647,7 +647,7 @@ struct XAigerWriter if (holes_module) { std::stringstream a_buffer; XAigerWriter writer(holes_module, false /* dff_mode */); - writer.write_aiger(a_buffer, false /*ascii_mode*/); + writer.write_aiger(a_buffer, false /*ascii_mode*/, ys_version); f << "a"; std::string buffer_str = a_buffer.str(); @@ -671,7 +671,8 @@ struct XAigerWriter //f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); //f.write(buffer_str.data(), buffer_str.size()); - f << stringf("Generated by %s\n", yosys_version_str); + if (ys_version) + f << stringf("Generated by %s\n", yosys_version_str); design->scratchpad_set_int("write_xaiger.num_ands", and_map.size()); design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size()); @@ -741,10 +742,13 @@ struct XAigerBackend : public Backend { log(" -dff\n"); log(" write $_DFF_[NP]_ cells\n"); log("\n"); + log(" -no_version\n"); + log(" don't write Yosys version\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { - bool ascii_mode = false, dff_mode = false; + bool ascii_mode = false, dff_mode = false, ys_version = true; std::string map_filename; log_header(design, "Executing XAIGER backend.\n"); @@ -764,6 +768,10 @@ struct XAigerBackend : public Backend { dff_mode = true; continue; } + if (args[argidx] == "-no_version") { + ys_version = false; + continue; + } break; } extra_args(f, filename, args, argidx, !ascii_mode); @@ -782,7 +790,7 @@ struct XAigerBackend : public Backend { log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module)); XAigerWriter writer(top_module, dff_mode); - writer.write_aiger(*f, ascii_mode); + writer.write_aiger(*f, ascii_mode, ys_version); if (!map_filename.empty()) { std::ofstream mapf; diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c7ed3b81f..23d26e378 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1310,6 +1310,9 @@ struct Aiger2Backend : Backend { log(" allow descending into submodules and write a flattened view of the design\n"); log(" hierarchy starting at the selected top\n"); log("\n"); + log(" -no_version\n"); + log(" don't write Yosys version\n"); + log("\n"); log("This command is able to ingest all combinational cells except for:\n"); log("\n"); pool supported = {KNOWN_OPS}; @@ -1353,15 +1356,21 @@ struct Aiger2Backend : Backend { size_t argidx; AigerWriter writer; writer.const_folding = true; + bool ys_version = true; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") writer.strashing = true; else if (args[argidx] == "-flatten") writer.flatten = true; + else if (args[argidx] == "-no_version") + ys_version = false; else break; } extra_args(f, filename, args, argidx); + // We don't actually ever print version yet, + // we have the arg just for consistency + (void)ys_version; Module *top = design->top_module(); @@ -1414,6 +1423,9 @@ struct XAiger2Backend : Backend { log(" reintegrate a mapping\n"); log(" (conflicts with -flatten)\n"); log("\n"); + log(" -no_version\n"); + log(" don't write Yosys version\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, Design *design) override @@ -1423,6 +1435,7 @@ struct XAiger2Backend : Backend { size_t argidx; XAigerWriter writer; std::string map_filename; + bool ys_version = true; writer.const_folding = true; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-strash") @@ -1433,10 +1446,15 @@ struct XAiger2Backend : Backend { writer.mapping_prep = true; else if (args[argidx] == "-map2" && argidx + 1 < args.size()) map_filename = args[++argidx]; + else if (args[argidx] == "-no_version") + ys_version = false; else break; } extra_args(f, filename, args, argidx); + // We don't actually ever print version yet, + // we have the arg just for consistency + (void)ys_version; Module *top = design->top_module();