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fix(parse): #5234 adjust width of rhs according to lhs

This commit is contained in:
rhanqtl 2025-09-04 23:19:11 +08:00 committed by Emil J. Tywoniak
parent c0577890f0
commit 11b829ba70
3 changed files with 32 additions and 1 deletions

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@ -0,0 +1,10 @@
read_verilog -sv <<EOF
module thing(input [2:0] in, output reg [2:0] out);
assign out = in;
endmodule
EOF
select -assert-count 0 t:$eq
fminit -set out 1'b1
select -assert-count 1 t:$eq
select -assert-count 1 t:$eq r:A_WIDTH=1 %i