fix(parse): #5234 adjust width of rhs according to lhs

tests/sat/fminit_noexpand.ys

@@ -0,0 +1,10 @@
+read_verilog -sv <<EOF
+module thing(input [2:0] in, output reg [2:0] out);
+    assign out = in;
+endmodule
+EOF
+
+select -assert-count 0 t:$eq
+fminit -set out 1'b1
+select -assert-count 1 t:$eq
+select -assert-count 1 t:$eq r:A_WIDTH=1 %i

tests/sat/fminit_seq_width.ys

@@ -0,0 +1,17 @@
+read_verilog -sv -formal <<EOF
+module counter(input clk, input [2:0] rst, input [0:3] rst_val, output logic is_full);
+    logic [1:0] ctr;
+
+    always @(posedge clk)
+        if (rst)
+            ctr <= 0;
+        else
+            ctr <= ctr+1;
+
+    assign is_full = (ctr == 2'b11);
+endmodule
+EOF
+
+hierarchy -check -top counter
+prep -top counter
+fminit -seq rst 0,1,2'b11,2'sb11,rst_val