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https://github.com/YosysHQ/yosys
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Add support for new FF types in some opt passes.
This commit is contained in:
Marcelina Kościelnicka
parent
b0bee396a8
commit
119f79d8b9
3 changed files with 53 additions and 14 deletions
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@ -467,15 +467,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (clkinv)
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{
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if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
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if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
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handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
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if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
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handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
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handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
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}
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if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
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handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
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handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($dffe), ID($adffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
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handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
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@ -489,12 +495,35 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
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@ -63,11 +63,13 @@ struct OnehotDatabase
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vector<SigSpec> inputs;
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SigSpec output;
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if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
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if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
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{
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output = cell->getPort(ID::Q);
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if (cell->type == ID($adff))
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
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inputs.push_back(cell->getParam(ID::ARST_VALUE));
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
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inputs.push_back(cell->getParam(ID::SRST_VALUE));
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inputs.push_back(cell->getPort(ID::D));
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}
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@ -39,7 +39,8 @@ struct WreduceConfig
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ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
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ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
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ID($mux), ID($pmux),
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ID($dff), ID($adff)
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ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
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ID($dlatch), ID($adlatch),
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});
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}
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};
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@ -143,8 +144,8 @@ struct WreduceWorker
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SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
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SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
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bool is_adff = (cell->type == ID($adff));
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Const initval, arst_value;
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bool has_reset = false;
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Const initval, rst_value;
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int width_before = GetSize(sig_q);
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@ -152,7 +153,11 @@ struct WreduceWorker
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return;
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if (cell->parameters.count(ID::ARST_VALUE)) {
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arst_value = cell->parameters[ID::ARST_VALUE];
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rst_value = cell->parameters[ID::ARST_VALUE];
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has_reset = true;
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} else if (cell->parameters.count(ID::SRST_VALUE)) {
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rst_value = cell->parameters[ID::SRST_VALUE];
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has_reset = true;
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}
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bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
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@ -169,7 +174,7 @@ struct WreduceWorker
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for (int i = GetSize(sig_q)-1; i >= 0; i--)
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{
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if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
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(!is_adff || i >= GetSize(arst_value) || arst_value[i] == State::S0 || arst_value[i] == State::Sx)) {
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(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
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module->connect(sig_q[i], State::S0);
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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@ -178,7 +183,7 @@ struct WreduceWorker
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}
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if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
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(!is_adff || i >= GetSize(arst_value) || arst_value[i] == arst_value[i-1])) {
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(!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
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module->connect(sig_q[i], sig_q[i-1]);
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remove_init_bits.insert(sig_q[i]);
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sig_d.remove(i);
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@ -221,8 +226,11 @@ struct WreduceWorker
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// Narrow ARST_VALUE parameter to new size.
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if (cell->parameters.count(ID::ARST_VALUE)) {
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arst_value.bits.resize(GetSize(sig_q));
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cell->setParam(ID::ARST_VALUE, arst_value);
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rst_value.bits.resize(GetSize(sig_q));
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cell->setParam(ID::ARST_VALUE, rst_value);
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} else if (cell->parameters.count(ID::SRST_VALUE)) {
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rst_value.bits.resize(GetSize(sig_q));
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cell->setParam(ID::SRST_VALUE, rst_value);
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}
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cell->setPort(ID::D, sig_d);
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@ -272,7 +280,7 @@ struct WreduceWorker
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if (cell->type.in(ID($mux), ID($pmux)))
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return run_cell_mux(cell);
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if (cell->type.in(ID($dff), ID($adff)))
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if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
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return run_cell_dff(cell);
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SigSpec sig = mi.sigmap(cell->getPort(ID::Y));
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