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Clean up pseudo-private member usage in passes/sat/expose.cc.

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Alberto Gonzalez 2020-03-28 06:18:09 +00:00
parent 1bf2bdf05b
commit 1197a43380
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GPG key ID: 8395A8BA109708B2
1 changed files with 9 additions and 11 deletions
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20
passes/sat/expose.cc
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@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{ {
if (cell->name[0] == '$' || dff_cells.count(cell->name)) if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false; return false;
if (cell->type[0] == '\\' && !design->modules_.count(cell->type)) if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
return false; return false;
return true; return true;
} }
@ -314,26 +314,26 @@ struct ExposePass : public Pass {
RTLIL::Module *first_module = NULL; RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires; std::set<RTLIL::IdString> shared_dff_wires;
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
{ {
if (!design->selected(mod_it.second)) if (!design->selected(mod))
continue; continue;
create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second); create_dff_dq_map(dff_dq_maps[mod], design, mod);
if (!flag_shared) if (!flag_shared)
continue; continue;
if (first_module == NULL) { if (first_module == NULL) {
for (auto &it : dff_dq_maps[mod_it.second]) for (auto &it : dff_dq_maps[mod])
shared_dff_wires.insert(it.first); shared_dff_wires.insert(it.first);
first_module = mod_it.second; first_module = mod;
} else { } else {
std::set<RTLIL::IdString> new_shared_dff_wires; std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) { for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod_it.second].count(it)) if (!dff_dq_maps[mod].count(it))
continue; continue;
if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it))) if (!compare_wires(first_module->wires_.at(it), mod->wires_.at(it)))
continue; continue;
new_shared_dff_wires.insert(it); new_shared_dff_wires.insert(it);
} }
@ -364,10 +364,8 @@ struct ExposePass : public Pass {
{ {
RTLIL::Module *first_module = NULL; RTLIL::Module *first_module = NULL;
for (auto &mod_it : design->modules_) for (auto module : design->modules())
{ {
RTLIL::Module *module = mod_it.second;
if (!design->selected(module)) if (!design->selected(module))
continue; continue;