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Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().

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This commit is contained in:
whitequark 2020-06-19 01:32:48 +00:00
parent 21692c4a2e
commit 118e4caa37
9 changed files with 26 additions and 26 deletions
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2
passes/opt/opt_expr.cc
View file

@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
}
void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
const std::string &info, IdString out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);

4
passes/techmap/abc9_ops.cc
View file

@ -741,7 +741,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (ys_debug(1))
toposort.analyze_loops = true;
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
bool no_loops = toposort.sort();
if (ys_debug(1)) {
unsigned i = 0;
@ -1453,7 +1453,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
bool no_loops = toposort.sort();
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {

10
passes/techmap/dfflibmap.cc
View file

@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
char from_clk_pol = from[8];
char from_set_pol = from[9];
char from_clr_pol = from[10];
char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
char to_clk_pol = to[6];
char to_rst_pol = to[7];
char to_rst_val = to[8];
log_assert(from_clk_pol == to_clk_pol);
@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
char from_clk_pol = from[6];
char from_rst_pol = from[7];
char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
char to_clk_pol = to[6];
log_assert(from_clk_pol == to_clk_pol);

4
passes/tests/test_abcloop.cc
View file

@ -132,7 +132,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
bool ok = satgen.importCell(c);
log_assert(ok);
}
@ -182,7 +182,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
bool ok = satgen.importCell(c);
log_assert(ok);
}