diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys
index 927d35c7b..3cc854c87 100644
--- a/tests/various/check_nolatches.ys
+++ b/tests/various/check_nolatches.ys
@@ -21,17 +21,6 @@ check -nolatches -assert
 
 design -reset
 
-read_verilog <<EOT
-module top(input g, rn, d, output reg q);
-always @* if (~rn) q <= 0; else if (g) q <= d;
-endmodule
-EOT
-proc
-logger -expect error "Found 1 problems in" 1
-check -nolatches -assert
-
-design -reset
-
 read_verilog <<EOT
 module top(input g, d, output reg q, output y);
 always @* if (g) q = d;
@@ -40,7 +29,5 @@ assign y = u;
 endmodule
 EOT
 proc
-logger -expect warning "is a latch of type" 1
-logger -expect warning "used but has no driver" 0
 logger -expect error "Found 1 problems in" 1
 check -latchonly -assert