mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

SigSpec refactoring: More cleanups of old SigSpec use pattern

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 23:50:21 +02:00
parent 9e94f41b89
commit 115dd959d9
3 changed files with 56 additions and 58 deletions
Download patch file Download diff file Expand all files Collapse all files

12
kernel/rtlil.cc
View file

@ -801,9 +801,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
for (auto &c : sig.chunks_rw())
std::vector<RTLIL::SigChunk> chunks = sig.chunks();
for (auto &c : chunks)
if (c.wire != NULL)
c.wire = mod->wires.at(c.wire->name);
sig = chunks;
}
};
@ -1469,6 +1471,14 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
check();
}
RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigChunk> chunks)
{
width_ = 0;
for (auto &c : chunks)
append(c);
check();
}
RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
{
width_ = 0;