mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-30 16:03:17 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
1123c09588
45 changed files with 6255 additions and 294 deletions
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@ -134,11 +134,11 @@ endmodule
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module RAM32X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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(* techmap_autopurge *) input D,
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(* techmap_autopurge *) input WCLK,
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(* techmap_autopurge *) input WE,
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(* techmap_autopurge *) input A0, A1, A2, A3, A4,
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(* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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parameter INIT = 32'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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@ -157,11 +157,11 @@ endmodule
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module RAM64X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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(* techmap_autopurge *) input D,
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(* techmap_autopurge *) input WCLK,
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(* techmap_autopurge *) input WE,
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(* techmap_autopurge *) input A0, A1, A2, A3, A4, A5,
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(* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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@ -180,10 +180,10 @@ endmodule
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module RAM128X1D (
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output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input [6:0] A, DPRA
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(* techmap_autopurge *) input D,
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(* techmap_autopurge *) input WCLK,
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(* techmap_autopurge *) input WE,
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(* techmap_autopurge *) input [6:0] A, DPRA
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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@ -202,7 +202,7 @@ endmodule
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module SRL16E (
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output Q,
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input A0, A1, A2, A3, CE, CLK, D
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(* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -219,8 +219,8 @@ endmodule
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module SRLC32E (
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output Q,
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output Q31,
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input [4:0] A,
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input CE, CLK, D
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(* techmap_autopurge *) input [4:0] A,
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(* techmap_autopurge *) input CE, CLK, D
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -233,3 +233,327 @@ module SRLC32E (
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);
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\$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
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endmodule
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module DSP48E1 (
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(* techmap_autopurge *) output [29:0] ACOUT,
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(* techmap_autopurge *) output [17:0] BCOUT,
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(* techmap_autopurge *) output reg CARRYCASCOUT,
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(* techmap_autopurge *) output reg [3:0] CARRYOUT,
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(* techmap_autopurge *) output reg MULTSIGNOUT,
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(* techmap_autopurge *) output OVERFLOW,
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(* techmap_autopurge *) output reg signed [47:0] P,
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(* techmap_autopurge *) output PATTERNBDETECT,
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(* techmap_autopurge *) output PATTERNDETECT,
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(* techmap_autopurge *) output [47:0] PCOUT,
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(* techmap_autopurge *) output UNDERFLOW,
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(* techmap_autopurge *) input signed [29:0] A,
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(* techmap_autopurge *) input [29:0] ACIN,
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(* techmap_autopurge *) input [3:0] ALUMODE,
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(* techmap_autopurge *) input signed [17:0] B,
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(* techmap_autopurge *) input [17:0] BCIN,
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(* techmap_autopurge *) input [47:0] C,
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(* techmap_autopurge *) input CARRYCASCIN,
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(* techmap_autopurge *) input CARRYIN,
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(* techmap_autopurge *) input [2:0] CARRYINSEL,
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(* techmap_autopurge *) input CEA1,
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(* techmap_autopurge *) input CEA2,
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(* techmap_autopurge *) input CEAD,
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(* techmap_autopurge *) input CEALUMODE,
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(* techmap_autopurge *) input CEB1,
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(* techmap_autopurge *) input CEB2,
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(* techmap_autopurge *) input CEC,
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(* techmap_autopurge *) input CECARRYIN,
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(* techmap_autopurge *) input CECTRL,
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(* techmap_autopurge *) input CED,
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(* techmap_autopurge *) input CEINMODE,
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(* techmap_autopurge *) input CEM,
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(* techmap_autopurge *) input CEP,
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(* techmap_autopurge *) input CLK,
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(* techmap_autopurge *) input [24:0] D,
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(* techmap_autopurge *) input [4:0] INMODE,
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(* techmap_autopurge *) input MULTSIGNIN,
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(* techmap_autopurge *) input [6:0] OPMODE,
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(* techmap_autopurge *) input [47:0] PCIN,
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(* techmap_autopurge *) input RSTA,
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(* techmap_autopurge *) input RSTALLCARRYIN,
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(* techmap_autopurge *) input RSTALUMODE,
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(* techmap_autopurge *) input RSTB,
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(* techmap_autopurge *) input RSTC,
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(* techmap_autopurge *) input RSTCTRL,
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(* techmap_autopurge *) input RSTD,
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(* techmap_autopurge *) input RSTINMODE,
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(* techmap_autopurge *) input RSTM,
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(* techmap_autopurge *) input RSTP
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);
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
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`define DSP48E1_INST(__CELL__) """
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__CELL__ #(
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.ACASCREG(ACASCREG),
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.ADREG(ADREG),
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.ALUMODEREG(ALUMODEREG),
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.AREG(AREG),
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.AUTORESET_PATDET(AUTORESET_PATDET),
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.A_INPUT(A_INPUT),
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.BCASCREG(BCASCREG),
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.BREG(BREG),
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.B_INPUT(B_INPUT),
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.CARRYINREG(CARRYINREG),
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.CARRYINSELREG(CARRYINSELREG),
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.CREG(CREG),
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.DREG(DREG),
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.INMODEREG(INMODEREG),
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.MREG(MREG),
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.OPMODEREG(OPMODEREG),
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.PREG(PREG),
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.SEL_MASK(SEL_MASK),
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.SEL_PATTERN(SEL_PATTERN),
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.USE_DPORT(USE_DPORT),
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.USE_MULT(USE_MULT),
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.USE_PATTERN_DETECT(USE_PATTERN_DETECT),
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.USE_SIMD(USE_SIMD),
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.MASK(MASK),
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.PATTERN(PATTERN),
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.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
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.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
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.IS_CLK_INVERTED(IS_CLK_INVERTED),
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.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
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.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
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) _TECHMAP_REPLACE_ (
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.ACOUT(ACOUT),
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.BCOUT(BCOUT),
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.CARRYCASCOUT(CARRYCASCOUT),
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.CARRYOUT(CARRYOUT),
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.MULTSIGNOUT(MULTSIGNOUT),
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.OVERFLOW(OVERFLOW),
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.P(oP),
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.PATTERNBDETECT(PATTERNBDETECT),
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.PATTERNDETECT(PATTERNDETECT),
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.PCOUT(oPCOUT),
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.UNDERFLOW(UNDERFLOW),
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.A(iA),
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.ACIN(ACIN),
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.ALUMODE(ALUMODE),
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.B(iB),
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.BCIN(BCIN),
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.C(iC),
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.CARRYCASCIN(CARRYCASCIN),
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.CARRYIN(CARRYIN),
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.CARRYINSEL(CARRYINSEL),
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.CEA1(CEA1),
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.CEA2(CEA2),
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.CEAD(CEAD),
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.CEALUMODE(CEALUMODE),
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.CEB1(CEB1),
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.CEB2(CEB2),
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.CEC(CEC),
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.CECARRYIN(CECARRYIN),
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.CECTRL(CECTRL),
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.CED(CED),
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.CEINMODE(CEINMODE),
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.CEM(CEM),
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.CEP(CEP),
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.CLK(CLK),
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.D(iD),
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.INMODE(INMODE),
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.MULTSIGNIN(MULTSIGNIN),
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.OPMODE(OPMODE),
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.PCIN(PCIN),
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.RSTA(RSTA),
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.RSTALLCARRYIN(RSTALLCARRYIN),
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.RSTALUMODE(RSTALUMODE),
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.RSTB(RSTB),
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.RSTC(RSTC),
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.RSTCTRL(RSTCTRL),
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.RSTD(RSTD),
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.RSTINMODE(RSTINMODE),
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.RSTM(RSTM),
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.RSTP(RSTP)
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);
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"""
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wire [29:0] iA;
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wire [17:0] iB;
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wire [47:0] iC;
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wire [24:0] iD;
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wire pA, pB, pC, pD, pAD, pM, pP;
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wire [47:0] oP, mP;
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wire [47:0] oPCOUT, mPCOUT;
|
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|
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generate
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if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
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||||
// Disconnect the A-input if MREG is enabled, since
|
||||
// combinatorial path is broken
|
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if (AREG == 0 && MREG == 0 && PREG == 0)
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assign iA = A, pA = 1'bx;
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else
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\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
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if (BREG == 0 && MREG == 0 && PREG == 0)
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assign iB = B, pB = 1'bx;
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else
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\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
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if (CREG == 0 && PREG == 0)
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assign iC = C, pC = 1'bx;
|
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else
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\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
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if (DREG == 0)
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assign iD = D;
|
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else if (techmap_guard)
|
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$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
|
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assign pD = 1'bx;
|
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if (ADREG == 1 && techmap_guard)
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$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
|
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assign pAD = 1'bx;
|
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if (PREG == 0) begin
|
||||
if (MREG == 1)
|
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\$__ABC_REG rM (.Q(pM));
|
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else
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assign pM = 1'bx;
|
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assign pP = 1'bx;
|
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end else begin
|
||||
assign pM = 1'bx;
|
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\$__ABC_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
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\$__ABC_DSP48E1_MULT_P_MUX muxP (
|
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.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_MULT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1_MULT )
|
||||
end
|
||||
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
// combinatorial path is broken
|
||||
if (AREG == 0 && ADREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && MREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 0 && ADREG == 0)
|
||||
assign iD = D, pD = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(25)) rD (.I(D), .O(iD), .Q(pD));
|
||||
if (PREG == 0) begin
|
||||
if (MREG == 1) begin
|
||||
assign pAD = 1'bx;
|
||||
\$__ABC_REG rM (.Q(pM));
|
||||
end else begin
|
||||
if (ADREG == 1)
|
||||
\$__ABC_REG rAD (.Q(pAD));
|
||||
else
|
||||
assign pAD = 1'bx;
|
||||
assign pM = 1'bx;
|
||||
end
|
||||
assign pP = 1'bx;
|
||||
end else begin
|
||||
assign pAD = 1'bx, pM = 1'bx;
|
||||
\$__ABC_REG rP (.Q(pP));
|
||||
end
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC_DSP48E1_MULT_DPORT_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1_MULT_DPORT )
|
||||
end
|
||||
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
|
||||
// Disconnect the A-input if MREG is enabled, since
|
||||
// combinatorial path is broken
|
||||
if (AREG == 0 && PREG == 0)
|
||||
assign iA = A, pA = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(30)) rA (.I(A), .O(iA), .Q(pA));
|
||||
if (BREG == 0 && PREG == 0)
|
||||
assign iB = B, pB = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(18)) rB (.I(B), .O(iB), .Q(pB));
|
||||
if (CREG == 0 && PREG == 0)
|
||||
assign iC = C, pC = 1'bx;
|
||||
else
|
||||
\$__ABC_REG #(.WIDTH(48)) rC (.I(C), .O(iC), .Q(pC));
|
||||
if (DREG == 1 && techmap_guard)
|
||||
$error("Invalid DSP48E1 configuration: DREG enabled but USE_DPORT == \"FALSE\"");
|
||||
assign pD = 1'bx;
|
||||
if (ADREG == 1 && techmap_guard)
|
||||
$error("Invalid DSP48E1 configuration: ADREG enabled but USE_DPORT == \"FALSE\"");
|
||||
assign pAD = 1'bx;
|
||||
if (MREG == 1 && techmap_guard)
|
||||
$error("Invalid DSP48E1 configuration: MREG enabled but USE_MULT == \"NONE\"");
|
||||
assign pM = 1'bx;
|
||||
if (PREG == 1)
|
||||
\$__ABC_REG rP (.Q(pP));
|
||||
else
|
||||
assign pP = 1'bx;
|
||||
|
||||
if (MREG == 0 && PREG == 0)
|
||||
assign mP = oP, mPCOUT = oPCOUT;
|
||||
else
|
||||
assign mP = 1'bx, mPCOUT = 1'bx;
|
||||
\$__ABC_DSP48E1_P_MUX muxP (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oP), .Mq(pM), .P(mP), .Pq(pP), .O(P)
|
||||
);
|
||||
\$__ABC_DSP48E1_PCOUT_MUX muxPCOUT (
|
||||
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .I(oPCOUT), .Mq(pM), .P(mPCOUT), .Pq(pP), .O(PCOUT)
|
||||
);
|
||||
|
||||
`DSP48E1_INST(\$__ABC_DSP48E1 )
|
||||
end
|
||||
else
|
||||
$error("Invalid DSP48E1 configuration");
|
||||
endgenerate
|
||||
`undef DSP48E1_INST
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue