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Revert "Optimise write_xaiger"

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Eddie Hung 2019-12-20 12:05:45 -08:00 • committed by GitHub
parent 319cba70d3
commit 10e82e103f
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4 changed files with 21 additions and 39 deletions
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5
techlibs/ice40/synth_ice40.cc
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@ -350,11 +350,6 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
run("wbflip @abc9_boxes");
run("techmap -autoproc @abc9_boxes");
run("aigmap @abc9_boxes");
run("wbflip @abc9_boxes");
run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")