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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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2
passes/techmap/dfflibmap.cc
View file

@ -524,7 +524,7 @@ struct DfflibmapPass : public Pass {
log(" final dff cell mappings:\n");
logmap_all();
for (auto &it : design->modules)
for (auto &it : design->modules_)
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
dfflibmap(design, it.second);

12
passes/techmap/extract.cc
View file

@ -604,9 +604,9 @@ struct ExtractPass : public Pass {
delete map;
log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
}
for (auto &it : saved_designs.at(filename.substr(1))->modules)
if (!map->modules.count(it.first))
map->modules[it.first] = it.second->clone();
for (auto &it : saved_designs.at(filename.substr(1))->modules_)
if (!map->modules_.count(it.first))
map->modules_[it.first] = it.second->clone();
}
else
{
@ -632,7 +632,7 @@ struct ExtractPass : public Pass {
log_header("Creating graphs for SubCircuit library.\n");
if (!mine_mode)
for (auto &mod_it : map->modules) {
for (auto &mod_it : map->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
log("Creating needle graph %s.\n", graph_name.c_str());
@ -643,7 +643,7 @@ struct ExtractPass : public Pass {
}
}
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
log("Creating haystack graph %s.\n", graph_name.c_str());
@ -725,7 +725,7 @@ struct ExtractPass : public Pass {
RTLIL::Module *newMod = new RTLIL::Module;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
map->modules[newMod->name] = newMod;
map->modules_[newMod->name] = newMod;
int portCounter = 1;
for (auto wire : wires) {

2
passes/techmap/hilomap.cc
View file

@ -104,7 +104,7 @@ struct HilomapPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &it : design->modules)
for (auto &it : design->modules_)
{
module = it.second;

2
passes/techmap/iopadmap.cc
View file

@ -111,7 +111,7 @@ struct IopadmapPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &it : design->modules)
for (auto &it : design->modules_)
{
RTLIL::Module *module = it.second;

2
passes/techmap/simplemap.cc
View file

@ -435,7 +435,7 @@ struct SimplemapPass : public Pass {
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;

22
passes/techmap/techmap.cc
View file

@ -243,7 +243,7 @@ struct TechmapWorker
for (auto &tpl_name : celltypeMap.at(cell->type))
{
std::string derived_name = tpl_name;
RTLIL::Module *tpl = map->modules[tpl_name];
RTLIL::Module *tpl = map->modules_[tpl_name];
std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
if (tpl->get_bool_attribute("\\blackbox"))
@ -334,7 +334,7 @@ struct TechmapWorker
} else {
if (cell->parameters.size() != 0) {
derived_name = tpl->derive(map, parameters);
tpl = map->modules[derived_name];
tpl = map->modules_[derived_name];
log_continue = true;
}
techmap_cache[key] = tpl;
@ -592,15 +592,15 @@ struct TechmapPass : public Pass {
}
std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
for (auto &it : map->modules) {
for (auto &it : map->modules_) {
if (it.first.substr(0, 2) == "\\$")
it.second->name = it.first.substr(1);
modules_new[it.second->name] = it.second;
}
map->modules.swap(modules_new);
map->modules_.swap(modules_new);
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
for (auto &it : map->modules) {
for (auto &it : map->modules_) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
@ -614,7 +614,7 @@ struct TechmapPass : public Pass {
std::set<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
did_something = true;
if (did_something)
@ -653,12 +653,12 @@ struct FlattenPass : public Pass {
TechmapWorker worker;
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
for (auto &it : design->modules)
for (auto &it : design->modules_)
celltypeMap[it.first].insert(it.first);
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
@ -670,7 +670,7 @@ struct FlattenPass : public Pass {
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true;
} else {
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
did_something = true;
}
@ -680,14 +680,14 @@ struct FlattenPass : public Pass {
if (top_mod != NULL) {
std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
new_modules[mod_it.first] = mod_it.second;
} else {
log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
delete mod_it.second;
}
design->modules.swap(new_modules);
design->modules_.swap(new_modules);
}
log_pop();