3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00

Refactoring: Renamed RTLIL::Design::modules to modules_

This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions

View file

@ -961,7 +961,7 @@ struct SharePass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
ShareWorker(config, design, mod_it.second);
}