mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-23 22:33:41 +00:00
Refactoring: Renamed RTLIL::Design::modules to modules_
This commit is contained in:
parent
d088854b47
commit
10e5791c5e
73 changed files with 223 additions and 223 deletions
|
@ -1141,7 +1141,7 @@ struct SatPass : public Pass {
|
|||
extra_args(args, argidx, design);
|
||||
|
||||
RTLIL::Module *module = NULL;
|
||||
for (auto &mod_it : design->modules)
|
||||
for (auto &mod_it : design->modules_)
|
||||
if (design->selected(mod_it.second)) {
|
||||
if (module)
|
||||
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n",
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue