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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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2
passes/sat/freduce.cc
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@ -817,7 +817,7 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
RTLIL::Module *module = mod_it.second;
if (design->selected(module))
bitcount += FreduceWorker(design, module).run();