mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-31 08:23:19 +00:00
Refactoring: Renamed RTLIL::Design::modules to modules_
This commit is contained in:
parent
d088854b47
commit
10e5791c5e
73 changed files with 223 additions and 223 deletions
|
@ -371,7 +371,7 @@ struct ProcDffPass : public Pass {
|
|||
|
||||
extra_args(args, 1, design);
|
||||
|
||||
for (auto &mod_it : design->modules)
|
||||
for (auto &mod_it : design->modules_)
|
||||
if (design->selected(mod_it.second)) {
|
||||
ConstEval ce(mod_it.second);
|
||||
for (auto &proc_it : mod_it.second->processes)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue