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Refactoring: Renamed RTLIL::Design::modules to modules_

This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions

View file

@ -236,7 +236,7 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
SigMap assign_map(mod_it.second);
for (auto &proc_it : mod_it.second->processes) {

View file

@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
std::vector<std::string> delme;
if (!design->selected(mod_it.second))
continue;

View file

@ -371,7 +371,7 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
ConstEval ce(mod_it.second);
for (auto &proc_it : mod_it.second->processes)

View file

@ -101,7 +101,7 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))

View file

@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))

View file

@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design);
int total_counter = 0;
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
for (auto &proc_it : mod_it.second->processes) {