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Refactoring: Renamed RTLIL::Design::modules to modules_
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parent
d088854b47
commit
10e5791c5e
73 changed files with 223 additions and 223 deletions
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@ -236,7 +236,7 @@ struct ProcArstPass : public Pass {
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second)) {
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SigMap assign_map(mod_it.second);
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for (auto &proc_it : mod_it.second->processes) {
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@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass {
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules) {
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for (auto &mod_it : design->modules_) {
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std::vector<std::string> delme;
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if (!design->selected(mod_it.second))
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continue;
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@ -371,7 +371,7 @@ struct ProcDffPass : public Pass {
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second)) {
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ConstEval ce(mod_it.second);
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for (auto &proc_it : mod_it.second->processes)
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@ -101,7 +101,7 @@ struct ProcInitPass : public Pass {
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto &proc_it : mod_it.second->processes)
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if (design->selected(mod_it.second, proc_it.second))
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@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass {
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto &proc_it : mod_it.second->processes)
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if (design->selected(mod_it.second, proc_it.second))
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@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass {
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extra_args(args, 1, design);
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int total_counter = 0;
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for (auto &mod_it : design->modules) {
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for (auto &mod_it : design->modules_) {
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if (!design->selected(mod_it.second))
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continue;
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for (auto &proc_it : mod_it.second->processes) {
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