mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-20 12:53:39 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/fsm/fsm_recode.cc
View file

@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))