mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/fsm/fsm_extract.cc
View file

@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass {
ct.setup_stdcells();
ct.setup_stdcells_mem();
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;