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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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2
passes/fsm/fsm_detect.cc
View file

@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass {
ct.setup_stdcells();
ct.setup_stdcells_mem();
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;

2
passes/fsm/fsm_expand.cc
View file

@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;

2
passes/fsm/fsm_export.cc
View file

@ -174,7 +174,7 @@ struct FsmExportPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {

2
passes/fsm/fsm_extract.cc
View file

@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass {
ct.setup_stdcells();
ct.setup_stdcells_mem();
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;

2
passes/fsm/fsm_info.cc
View file

@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass {
log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {

2
passes/fsm/fsm_map.cc
View file

@ -309,7 +309,7 @@ struct FsmMapPass : public Pass {
log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;

2
passes/fsm/fsm_opt.cc
View file

@ -288,7 +288,7 @@ struct FsmOptPass : public Pass {
log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))

2
passes/fsm/fsm_recode.cc
View file

@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))