mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-29 20:59:03 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/setundef.cc
View file

@ -115,7 +115,7 @@ struct SetundefPass : public Pass {
if (!got_value)
log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))