mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-16 14:41:33 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/setattr.cc
View file

@ -98,7 +98,7 @@ struct SetattrPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
@ -164,7 +164,7 @@ struct SetparamPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;