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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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6
passes/cmds/add.cc
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@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
for (auto &it : module->cells_)
{
if (design->modules.count(it.second->type) == 0)
if (design->modules_.count(it.second->type) == 0)
continue;
RTLIL::Module *mod = design->modules.at(it.second->type);
RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\blackbox"))
@ -136,7 +136,7 @@ struct AddPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))