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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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6
passes/cmds/add.cc
View file

@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
for (auto &it : module->cells_)
{
if (design->modules.count(it.second->type) == 0)
if (design->modules_.count(it.second->type) == 0)
continue;
RTLIL::Module *mod = design->modules.at(it.second->type);
RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\blackbox"))
@ -136,7 +136,7 @@ struct AddPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))

2
passes/cmds/connect.cc
View file

@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
RTLIL::Module *module = NULL;
for (auto &it : design->modules) {
for (auto &it : design->modules_) {
if (!design->selected(it.second))
continue;
if (module != NULL)

2
passes/cmds/connwrappers.cc
View file

@ -197,7 +197,7 @@ struct ConnwrappersPass : public Pass {
log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
worker.work(design, mod_it.second);
}

8
passes/cmds/copy.cc
View file

@ -41,14 +41,14 @@ struct CopyPass : public Pass {
std::string src_name = RTLIL::escape_id(args[1]);
std::string trg_name = RTLIL::escape_id(args[2]);
if (design->modules.count(src_name) == 0)
if (design->modules_.count(src_name) == 0)
log_cmd_error("Can't find source module %s.\n", src_name.c_str());
if (design->modules.count(trg_name) != 0)
if (design->modules_.count(trg_name) != 0)
log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
design->modules[trg_name] = design->modules.at(src_name)->clone();
design->modules[trg_name]->name = trg_name;
design->modules_[trg_name] = design->modules_.at(src_name)->clone();
design->modules_[trg_name]->name = trg_name;
}
} CopyPass;

6
passes/cmds/delete.cc
View file

@ -66,7 +66,7 @@ struct DeletePass : public Pass {
std::vector<std::string> delete_mods;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
delete_mods.push_back(mod_it.first);
@ -134,8 +134,8 @@ struct DeletePass : public Pass {
}
for (auto &it : delete_mods) {
delete design->modules.at(it);
design->modules.erase(it);
delete design->modules_.at(it);
design->modules_.erase(it);
}
}
} DeletePass;

22
passes/cmds/design.cc
View file

@ -165,7 +165,7 @@ struct DesignPass : public Pass {
argidx = args.size();
}
for (auto &it : copy_from_design->modules) {
for (auto &it : copy_from_design->modules_) {
if (sel.selected_whole_module(it.first)) {
copy_src_modules.push_back(it.second);
continue;
@ -192,10 +192,10 @@ struct DesignPass : public Pass {
{
std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name);
if (copy_to_design->modules.count(trg_name))
delete copy_to_design->modules.at(trg_name);
copy_to_design->modules[trg_name] = mod->clone();
copy_to_design->modules[trg_name]->name = trg_name;
if (copy_to_design->modules_.count(trg_name))
delete copy_to_design->modules_.at(trg_name);
copy_to_design->modules_[trg_name] = mod->clone();
copy_to_design->modules_[trg_name]->name = trg_name;
}
}
@ -203,8 +203,8 @@ struct DesignPass : public Pass {
{
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto &it : design->modules)
design_copy->modules[it.first] = it.second->clone();
for (auto &it : design->modules_)
design_copy->modules_[it.first] = it.second->clone();
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
@ -221,9 +221,9 @@ struct DesignPass : public Pass {
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
{
for (auto &it : design->modules)
for (auto &it : design->modules_)
delete it.second;
design->modules.clear();
design->modules_.clear();
design->selection_stack.clear();
design->selection_vars.clear();
@ -239,8 +239,8 @@ struct DesignPass : public Pass {
if (pop_mode)
pushed_designs.pop_back();
for (auto &it : saved_design->modules)
design->modules[it.first] = it.second->clone();
for (auto &it : saved_design->modules_)
design->modules_[it.first] = it.second->clone();
design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars;

14
passes/cmds/rename.cc
View file

@ -96,7 +96,7 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
int counter = 0;
@ -128,7 +128,7 @@ struct RenamePass : public Pass {
{
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected(module))
@ -163,19 +163,19 @@ struct RenamePass : public Pass {
if (!design->selected_active_module.empty())
{
if (design->modules.count(design->selected_active_module) > 0)
rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name);
if (design->modules_.count(design->selected_active_module) > 0)
rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
}
else
{
for (auto &mod : design->modules) {
for (auto &mod : design->modules_) {
if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
RTLIL::Module *module = mod.second;
design->modules.erase(module->name);
design->modules_.erase(module->name);
module->name = to_name;
design->modules[module->name] = module;
design->modules_[module->name] = module;
goto rename_ok;
}
}

2
passes/cmds/scatter.cc
View file

@ -43,7 +43,7 @@ struct ScatterPass : public Pass {
CellTypes ct(design);
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;

2
passes/cmds/scc.cc
View file

@ -280,7 +280,7 @@ struct SccPass : public Pass {
RTLIL::Selection newSelection(false);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
{
SccWorker worker(design, mod_it.second, allCellTypes, maxDepth);

40
passes/cmds/select.cc
View file

@ -151,7 +151,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
RTLIL::Selection new_sel(false);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
continue;
@ -181,13 +181,13 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
{
for (auto &cell_it : mod_it.second->cells_)
{
if (design->modules.count(cell_it.second->type) == 0)
if (design->modules_.count(cell_it.second->type) == 0)
continue;
lhs.selected_modules.insert(cell_it.second->type);
}
@ -205,7 +205,7 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs)
static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
{
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
continue;
@ -260,7 +260,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
return;
lhs.full_selection = false;
for (auto &it : design->modules)
for (auto &it : design->modules_)
lhs.selected_modules.insert(it.first);
}
@ -271,10 +271,10 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
for (auto &it : rhs.selected_members)
{
if (design->modules.count(it.first) == 0)
if (design->modules_.count(it.first) == 0)
continue;
RTLIL::Module *mod = design->modules[it.first];
RTLIL::Module *mod = design->modules_[it.first];
if (lhs.selected_modules.count(mod->name) > 0)
{
@ -304,7 +304,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
if (lhs.full_selection) {
lhs.full_selection = false;
for (auto &it : design->modules)
for (auto &it : design->modules_)
lhs.selected_modules.insert(it.first);
}
@ -368,7 +368,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
{
int sel_objects = 0;
bool is_input, is_output;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first))
continue;
@ -684,7 +684,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
}
sel.full_selection = false;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (arg_mod.substr(0, 2) == "A:") {
if (!match_attr(mod_it.second->attributes, arg_mod.substr(2)))
@ -1078,7 +1078,7 @@ struct SelectPass : public Pass {
}
if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
if (design->modules.count(mod_name) == 0)
if (design->modules_.count(mod_name) == 0)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
design->selected_active_module = mod_name;
got_module = true;
@ -1147,7 +1147,7 @@ struct SelectPass : public Pass {
if (work_stack.size() > 0)
sel = &work_stack.back();
sel->optimize(design);
for (auto mod_it : design->modules)
for (auto mod_it : design->modules_)
{
if (sel->selected_whole_module(mod_it.first) && list_mode)
log("%s\n", id2cstr(mod_it.first));
@ -1217,7 +1217,7 @@ struct SelectPass : public Pass {
log_cmd_error("No selection to check.\n");
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
for (auto mod_it : design->modules)
for (auto mod_it : design->modules_)
if (sel->selected_module(mod_it.first)) {
for (auto &it : mod_it.second->wires_)
if (sel->selected_member(mod_it.first, it.first))
@ -1299,15 +1299,15 @@ struct CdPass : public Pass {
std::string modname = RTLIL::escape_id(args[1]);
if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) {
if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) {
RTLIL::Module *module = NULL;
if (design->modules.count(design->selected_active_module) > 0)
module = design->modules.at(design->selected_active_module);
if (design->modules_.count(design->selected_active_module) > 0)
module = design->modules_.at(design->selected_active_module);
if (module != NULL && module->cells_.count(modname) > 0)
modname = module->cells_.at(modname)->type;
}
if (design->modules.count(modname) > 0) {
if (design->modules_.count(modname) > 0) {
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
@ -1368,12 +1368,12 @@ struct LsPass : public Pass {
if (design->selected_active_module.empty())
{
counter += log_matches("modules", pattern, design->modules);
counter += log_matches("modules", pattern, design->modules_);
}
else
if (design->modules.count(design->selected_active_module) > 0)
if (design->modules_.count(design->selected_active_module) > 0)
{
RTLIL::Module *module = design->modules.at(design->selected_active_module);
RTLIL::Module *module = design->modules_.at(design->selected_active_module);
counter += log_matches("wires", pattern, module->wires_);
counter += log_matches("memories", pattern, module->memories);
counter += log_matches("cells", pattern, module->cells_);

4
passes/cmds/setattr.cc
View file

@ -98,7 +98,7 @@ struct SetattrPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
@ -164,7 +164,7 @@ struct SetparamPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod : design->modules)
for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;

2
passes/cmds/setundef.cc
View file

@ -115,7 +115,7 @@ struct SetundefPass : public Pass {
if (!got_value)
log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))

4
passes/cmds/show.cc
View file

@ -506,7 +506,7 @@ struct ShowWorker
design->optimize();
page_counter = 0;
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
module = mod_it.second;
if (!design->selected_module(module->name))
@ -692,7 +692,7 @@ struct ShowPass : public Pass {
if (format != "ps") {
int modcount = 0;
for (auto &mod_it : design->modules) {
for (auto &mod_it : design->modules_) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())

2
passes/cmds/splice.cc
View file

@ -327,7 +327,7 @@ struct SplicePass : public Pass {
log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;

2
passes/cmds/splitnets.cc
View file

@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules)
for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))

6
passes/cmds/stat.cc
View file

@ -166,16 +166,16 @@ struct StatPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
if (design->modules.count(RTLIL::escape_id(args[argidx+1])) == 0)
if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0)
log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
top_mod = design->modules.at(RTLIL::escape_id(args[++argidx]));
top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx]));
continue;
}
break;
}
extra_args(args, argidx, design);
for (auto &it : design->modules)
for (auto &it : design->modules_)
{
if (!design->selected_module(it.first))
continue;