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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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10
frontends/ast/ast.cc
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@ -931,7 +931,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str = (*it)->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
if (design->modules.count((*it)->str)) {
if (design->modules_.count((*it)->str)) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@ -939,7 +939,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
design->modules[(*it)->str] = process_module(*it, defer);
design->modules_[(*it)->str] = process_module(*it, defer);
}
}
@ -1036,10 +1036,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
modname = "$paramod" + stripped_name + para_info;
}
if (design->modules.count(modname) == 0) {
if (design->modules_.count(modname) == 0) {
new_ast->str = modname;
design->modules[modname] = process_module(new_ast, false);
design->modules[modname]->check();
design->modules_[modname] = process_module(new_ast, false);
design->modules_[modname]->check();
} else {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}