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Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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2
backends/verilog/verilog_backend.cc
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@ -1055,7 +1055,7 @@ struct VerilogBackend : public Backend {
extra_args(f, filename, args, argidx);
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {