mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-10 08:03:26 +00:00
Refactoring: Renamed RTLIL::Design::modules to modules_
This commit is contained in:
parent
d088854b47
commit
10e5791c5e
73 changed files with 223 additions and 223 deletions
|
@ -339,7 +339,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
|
|||
|
||||
if (!flag_m) {
|
||||
int count_selected_mods = 0;
|
||||
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
|
||||
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
|
||||
if (design->selected_whole_module(it->first))
|
||||
flag_m = true;
|
||||
if (design->selected(it->second))
|
||||
|
@ -355,7 +355,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
|
|||
fprintf(f, "autoidx %d\n", RTLIL::autoidx);
|
||||
}
|
||||
|
||||
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
|
||||
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
|
||||
if (!only_selected || design->selected(it->second)) {
|
||||
if (only_selected)
|
||||
fprintf(f, "\n");
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue