mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 14:53:42 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/btor/btor.cc
View file

@ -964,7 +964,7 @@ struct BtorBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
for (auto & mod_it:design->modules)
for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
@ -975,7 +975,7 @@ struct BtorBackend : public Backend {
std::vector<RTLIL::Module*> mod_list;
for (auto module_it : design->modules)
for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))