mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-11 17:54:44 +00:00
Code Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
Download patch file Download diff file Expand all files Collapse all files

4
backends/autotest/autotest.cc
View file

@ -91,7 +91,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
for (auto it = design->modules.begin(); it != design->modules.end(); it++)
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
{
std::map<std::string, int> signal_in;
std::map<std::string, std::string> signal_const;
@ -292,7 +292,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "initial begin\n");
fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
fprintf(f, "\t// $dumpvars(0, testbench);\n");
for (auto it = design->modules.begin(); it != design->modules.end(); it++)
for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
if (!it->second->get_bool_attribute("\\gentb_skip"))
fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
fprintf(f, "\t$finish;\n");