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rtlil: extend SigSpec::extract test

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This commit is contained in:
Emil J. Tywoniak 2026-04-24 11:03:02 +02:00
parent a2dafce910
commit 10bbda93f7
2 changed files with 52 additions and 21 deletions
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70
tests/unit/kernel/sigspecExtractTest.cc
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@ -6,38 +6,52 @@
YOSYS_NAMESPACE_BEGIN
namespace RTLIL {
TEST_F(SigSpecRepTest, ExtractWires)
{
auto wires = createWires(4, 4);
SigSpec sig = wiresAsSigSpec(wires);
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(12, 4);
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
}
TEST_F(SigSpecRepTest, ExtractConsts)
TEST_F(SigSpecRepTest, Extract)
{
{
SigSpec sig = constsAsSigSpec(4, 4);
std::vector<Wire*> wires;
SigSpec sig;
for (int i = 0; i < 4; i++)
wires.push_back(m->addWire(stringf("$w%d", i), 4));
for (auto w : wires)
sig.append(w);
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(12, 4);
std::cout << log_signal(extractedFirst) << "\n";
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedFirst.as_wire(), wires[0]);
EXPECT_EQ(extractedSecond.as_wire(), wires[1]);
EXPECT_EQ(extractedLast.as_wire(), wires[3]);
}
{
std::vector<SigSpec> consts;
SigSpec sig;
for (int i = 0; i < 4; i++)
consts.push_back(Const(i, 4));
for (auto c : consts)
sig.append(c);
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
SigSpec extractedLast = sig.extract(12, 4);
EXPECT_EQ(extractedFirst.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedSecond.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedLast.rep_, SigSpec::Representation::CHUNK);
EXPECT_EQ(extractedFirst, consts[0]);
EXPECT_EQ(extractedSecond, consts[1]);
EXPECT_EQ(extractedLast, consts[3]);
}
{
SigSpec sig;
sig.append(Const(0, 4));
sig.append(m->addWire("$foo", 4));
sig.append(Const(0, 4));
Wire* w = m->addWire("$foo", 4);
sig.append(w);
sig.append(Const(15, 4));
SigSpec extractedFirst = sig.extract(0, 4);
SigSpec extractedSecond = sig.extract(4, 4);
@ -48,8 +62,26 @@ namespace RTLIL {
SigSpec extractedFirstTwo = sig.extract(0, 8);
EXPECT_EQ(extractedFirstTwo.rep_, SigSpec::Representation::BITS);
SigSpec extractedLastTwo = sig.extract(0, 8);
SigSpec extractedLastTwo = sig.extract(4, 8);
EXPECT_EQ(extractedLastTwo.rep_, SigSpec::Representation::BITS);
EXPECT_EQ(extractedFirstTwo[0], State::S0);
EXPECT_EQ(extractedFirstTwo[1], State::S0);
EXPECT_EQ(extractedFirstTwo[2], State::S0);
EXPECT_EQ(extractedFirstTwo[3], State::S0);
EXPECT_EQ(extractedFirstTwo[4], SigBit(w, 0));
EXPECT_EQ(extractedFirstTwo[5], SigBit(w, 1));
EXPECT_EQ(extractedFirstTwo[6], SigBit(w, 2));
EXPECT_EQ(extractedFirstTwo[7], SigBit(w, 3));
EXPECT_EQ(extractedLastTwo[0], SigBit(w, 0));
EXPECT_EQ(extractedLastTwo[1], SigBit(w, 1));
EXPECT_EQ(extractedLastTwo[2], SigBit(w, 2));
EXPECT_EQ(extractedLastTwo[3], SigBit(w, 3));
EXPECT_EQ(extractedLastTwo[4], State::S1);
EXPECT_EQ(extractedLastTwo[5], State::S1);
EXPECT_EQ(extractedLastTwo[6], State::S1);
EXPECT_EQ(extractedLastTwo[7], State::S1);
}
}
};