From 10bb0f472fd2ccd6e28b63e20189ce1922ec7ceb Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Fri, 30 May 2025 21:43:33 -0600 Subject: [PATCH] docs: mention related effects for multiplexers in the cell library. --- docs/source/cell/word_mux.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/cell/word_mux.rst b/docs/source/cell/word_mux.rst index 3eca310f3..234d1016b 100644 --- a/docs/source/cell/word_mux.rst +++ b/docs/source/cell/word_mux.rst @@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\ 'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of the ``B`` input is sent to the output. When more than one bit from ``S`` is set the output is undefined. Cells of this type are used to model "parallel cases" -(defined by using the ``parallel_case`` attribute or detected by an -optimization). +(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0`` +SystemVerilog keywords, or detected by an optimization). The `$tribuf` cell is used to implement tristate logic. Cells of this type have a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A``