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verilog: fix sizing of ports with int types in module headers

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Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
This commit is contained in:
Zachary Snow 2021-03-01 13:31:25 -05:00
parent 1ec5994100
commit 10a6bc9b81
3 changed files with 64 additions and 2 deletions
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5
frontends/verilog/verilog_parser.y
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@ -546,8 +546,9 @@ module_arg:
node->str = *$4;
SET_AST_NODE_LOC(node, @4, @4);
node->port_id = ++port_counter;
if ($3 != NULL)
node->children.push_back($3);
AstNode *range = checkRange(node, $3);
if (range != NULL)
node->children.push_back(range);
if (!node->is_input && !node->is_output)
frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
if (node->is_reg && node->is_input && !node->is_output && !sv_mode)