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Merge pull request #4706 from povik/keep_hierarchy-adjustalgo

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Adjust `keep_hierarchy` behavior
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Martin Povišer 2024-12-03 12:18:28 +01:00 • committed by GitHub
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3 changed files with 131 additions and 15 deletions
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@ -370,6 +370,11 @@ Verilog Attributes and non-standard features
- The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten``
command from flattening the indicated cells and modules.
- The `gate_cost_equivalent` attribute on a module can be used to specify
the estimated cost of the module as a number of basic gate instances. See
the help message of command `keep_hierarchy` which interprets this
attribute.
- The ``init`` attribute on wires is set by the frontend when a register is
initialized "FPGA-style" with ``reg foo = val``. It can be used during
synthesis to add the necessary reset logic.
@ -591,7 +596,6 @@ Non-standard or SystemVerilog features for formal verification
``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
is marked with the ``(* gclk *)`` Verilog attribute.
Supported features from SystemVerilog
=====================================