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Add new tests for Efinix architecture.

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Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
This commit is contained in:
SergeyDegtyar 2019-09-23 15:51:41 +03:00
parent 7e8f7f4c59
commit 1070f2e90b
31 changed files with 710 additions and 0 deletions
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tests/efinix/memory.ys Normal file
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read_verilog memory.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#ERROR: Called with -verify and proof did fail!
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_RAM_5K
select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D