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Add new tests for Efinix architecture.

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Problems/questions:
	- fsm.ys. equiv_opt -assert failed because of unproven cells;
	- latches.ys,tribuf.ys - internal cells present;
	- memory.ys - sat called with -verify and proof did fail.
This commit is contained in:
SergeyDegtyar 2019-09-23 15:51:41 +03:00
parent 7e8f7f4c59
commit 1070f2e90b
31 changed files with 710 additions and 0 deletions
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tests/efinix/logic.ys Normal file
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read_verilog logic.v
hierarchy -top top
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D