mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-15 13:28:59 +00:00
Code Activity

Trim Y_WIDTH

Browse source
This commit is contained in:
Eddie Hung 2019-08-01 14:33:16 -07:00
parent 65de9aaaa9
commit 105aaeaf59
1 changed files with 3 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
techlibs/common/mul2dsp.v
View file

@ -56,20 +56,18 @@ module \$mul (A, B, Y);
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here // NB: A_SIGNED == B_SIGNED from here
`ifdef DSP_SIGNEDONLY `ifdef DSP_SIGNEDONLY
else if (!A_SIGNED) begin else if (!A_SIGNED)
wire [1:0] _;
\$mul #( \$mul #(
.A_SIGNED(1), .A_SIGNED(1),
.B_SIGNED(1), .B_SIGNED(1),
.A_WIDTH(A_WIDTH + 1), .A_WIDTH(A_WIDTH + 1),
.B_WIDTH(B_WIDTH + 1), .B_WIDTH(B_WIDTH + 1),
.Y_WIDTH(Y_WIDTH + 2) .Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.A({1'b0, A}), .A({1'b0, A}),
.B({1'b0, B}), .B({1'b0, B}),
.Y({_, Y}) .Y(Y)
); );
end
`endif `endif
else if (A_WIDTH < B_WIDTH) else if (A_WIDTH < B_WIDTH)
\$mul #( \$mul #(