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xilinx: Add models for LUTRAM cells. (#1537)
This commit is contained in:
Marcin Kościelnicki
GitHub
parent
2ec6d832dc
commit
10014e2643
3 changed files with 831 additions and 624 deletions
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@ -471,6 +471,473 @@ module LDPE (
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else if (GE && g) Q = D;
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endmodule
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// LUTRAM.
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// Single port.
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module RAM16X1S (
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output O,
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input A0, A1, A2, A3,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [3:0] a = {A3, A2, A1, A0};
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reg [15:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM16X1S_1 (
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output O,
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input A0, A1, A2, A3,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [3:0] a = {A3, A2, A1, A0};
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reg [15:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(negedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM32X1S (
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output O,
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input A0, A1, A2, A3, A4,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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reg [31:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM32X1S_1 (
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output O,
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input A0, A1, A2, A3, A4,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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reg [31:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(negedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM64X1S (
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output O,
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input A0, A1, A2, A3, A4, A5,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [63:0] INIT = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [5:0] a = {A5, A4, A3, A2, A1, A0};
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reg [63:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM64X1S_1 (
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output O,
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input A0, A1, A2, A3, A4, A5,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [63:0] INIT = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [5:0] a = {A5, A4, A3, A2, A1, A0};
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reg [63:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(negedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM128X1S (
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output O,
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input A0, A1, A2, A3, A4, A5, A6,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [127:0] INIT = 128'h00000000000000000000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
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reg [127:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM128X1S_1 (
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output O,
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input A0, A1, A2, A3, A4, A5, A6,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [127:0] INIT = 128'h00000000000000000000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
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reg [127:0] mem = INIT;
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assign O = mem[a];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(negedge clk) if (WE) mem[a] <= D;
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endmodule
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module RAM256X1S (
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output O,
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input [7:0] A,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [255:0] INIT = 256'h0;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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reg [255:0] mem = INIT;
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assign O = mem[A];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[A] <= D;
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endmodule
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module RAM512X1S (
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output O,
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input [8:0] A,
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input D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [511:0] INIT = 512'h0;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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reg [511:0] mem = INIT;
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assign O = mem[A];
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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always @(posedge clk) if (WE) mem[A] <= D;
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endmodule
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// Single port, wide.
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module RAM16X2S (
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output O0, O1,
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input A0, A1, A2, A3,
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input D0, D1,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [15:0] INIT_00 = 16'h0000;
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parameter [15:0] INIT_01 = 16'h0000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [3:0] a = {A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [15:0] mem0 = INIT_00;
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reg [15:0] mem1 = INIT_01;
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assign O0 = mem0[a];
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assign O1 = mem1[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D0;
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mem1[a] <= D1;
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end
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endmodule
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module RAM32X2S (
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output O0, O1,
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input A0, A1, A2, A3, A4,
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input D0, D1,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [31:0] INIT_00 = 32'h00000000;
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parameter [31:0] INIT_01 = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [31:0] mem0 = INIT_00;
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reg [31:0] mem1 = INIT_01;
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assign O0 = mem0[a];
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assign O1 = mem1[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D0;
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mem1[a] <= D1;
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end
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endmodule
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module RAM64X2S (
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output O0, O1,
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input A0, A1, A2, A3, A4, A5,
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input D0, D1,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [63:0] INIT_00 = 64'h0000000000000000;
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parameter [63:0] INIT_01 = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [5:0] a = {A5, A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [63:0] mem0 = INIT_00;
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reg [63:0] mem1 = INIT_01;
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assign O0 = mem0[a];
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assign O1 = mem1[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D0;
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mem1[a] <= D1;
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end
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endmodule
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module RAM16X4S (
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output O0, O1, O2, O3,
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input A0, A1, A2, A3,
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input D0, D1, D2, D3,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [15:0] INIT_00 = 16'h0000;
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parameter [15:0] INIT_01 = 16'h0000;
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parameter [15:0] INIT_02 = 16'h0000;
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parameter [15:0] INIT_03 = 16'h0000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [3:0] a = {A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [15:0] mem0 = INIT_00;
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reg [15:0] mem1 = INIT_01;
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reg [15:0] mem2 = INIT_02;
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reg [15:0] mem3 = INIT_03;
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assign O0 = mem0[a];
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assign O1 = mem1[a];
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assign O2 = mem2[a];
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assign O3 = mem3[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D0;
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mem1[a] <= D1;
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mem2[a] <= D2;
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mem3[a] <= D3;
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end
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endmodule
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module RAM32X4S (
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output O0, O1, O2, O3,
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input A0, A1, A2, A3, A4,
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input D0, D1, D2, D3,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [31:0] INIT_00 = 32'h00000000;
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parameter [31:0] INIT_01 = 32'h00000000;
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parameter [31:0] INIT_02 = 32'h00000000;
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parameter [31:0] INIT_03 = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [31:0] mem0 = INIT_00;
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reg [31:0] mem1 = INIT_01;
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reg [31:0] mem2 = INIT_02;
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reg [31:0] mem3 = INIT_03;
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assign O0 = mem0[a];
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assign O1 = mem1[a];
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assign O2 = mem2[a];
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assign O3 = mem3[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D0;
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mem1[a] <= D1;
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mem2[a] <= D2;
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mem3[a] <= D3;
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end
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endmodule
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module RAM16X8S (
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output [7:0] O,
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input A0, A1, A2, A3,
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input [7:0] D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [15:0] INIT_00 = 16'h0000;
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parameter [15:0] INIT_01 = 16'h0000;
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parameter [15:0] INIT_02 = 16'h0000;
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parameter [15:0] INIT_03 = 16'h0000;
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parameter [15:0] INIT_04 = 16'h0000;
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parameter [15:0] INIT_05 = 16'h0000;
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parameter [15:0] INIT_06 = 16'h0000;
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parameter [15:0] INIT_07 = 16'h0000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [3:0] a = {A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [15:0] mem0 = INIT_00;
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reg [15:0] mem1 = INIT_01;
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reg [15:0] mem2 = INIT_02;
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reg [15:0] mem3 = INIT_03;
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reg [15:0] mem4 = INIT_04;
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reg [15:0] mem5 = INIT_05;
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reg [15:0] mem6 = INIT_06;
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reg [15:0] mem7 = INIT_07;
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assign O[0] = mem0[a];
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assign O[1] = mem1[a];
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assign O[2] = mem2[a];
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assign O[3] = mem3[a];
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assign O[4] = mem4[a];
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assign O[5] = mem5[a];
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assign O[6] = mem6[a];
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assign O[7] = mem7[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D[0];
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mem1[a] <= D[1];
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mem2[a] <= D[2];
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mem3[a] <= D[3];
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mem4[a] <= D[4];
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mem5[a] <= D[5];
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mem6[a] <= D[6];
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mem7[a] <= D[7];
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end
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endmodule
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module RAM32X8S (
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output [7:0] O,
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input A0, A1, A2, A3, A4,
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input [7:0] D,
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(* clkbuf_sink *)
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(* invertible_pin = "IS_WCLK_INVERTED" *)
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input WCLK,
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input WE
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);
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parameter [31:0] INIT_00 = 32'h00000000;
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parameter [31:0] INIT_01 = 32'h00000000;
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parameter [31:0] INIT_02 = 32'h00000000;
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parameter [31:0] INIT_03 = 32'h00000000;
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parameter [31:0] INIT_04 = 32'h00000000;
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parameter [31:0] INIT_05 = 32'h00000000;
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parameter [31:0] INIT_06 = 32'h00000000;
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parameter [31:0] INIT_07 = 32'h00000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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wire [4:0] a = {A4, A3, A2, A1, A0};
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wire clk = WCLK ^ IS_WCLK_INVERTED;
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reg [31:0] mem0 = INIT_00;
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reg [31:0] mem1 = INIT_01;
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reg [31:0] mem2 = INIT_02;
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reg [31:0] mem3 = INIT_03;
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reg [31:0] mem4 = INIT_04;
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reg [31:0] mem5 = INIT_05;
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reg [31:0] mem6 = INIT_06;
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reg [31:0] mem7 = INIT_07;
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assign O[0] = mem0[a];
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assign O[1] = mem1[a];
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assign O[2] = mem2[a];
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assign O[3] = mem3[a];
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assign O[4] = mem4[a];
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assign O[5] = mem5[a];
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assign O[6] = mem6[a];
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assign O[7] = mem7[a];
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always @(posedge clk)
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if (WE) begin
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mem0[a] <= D[0];
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mem1[a] <= D[1];
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mem2[a] <= D[2];
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mem3[a] <= D[3];
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mem4[a] <= D[4];
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mem5[a] <= D[5];
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mem6[a] <= D[6];
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mem7[a] <= D[7];
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end
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endmodule
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// Dual port.
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module RAM16X1D (
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output DPO, SPO,
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input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3
|
||||
);
|
||||
parameter INIT = 16'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire [3:0] a = {A3, A2, A1, A0};
|
||||
wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
|
||||
reg [15:0] mem = INIT;
|
||||
assign SPO = mem[a];
|
||||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM16X1D_1 (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3
|
||||
);
|
||||
parameter INIT = 16'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire [3:0] a = {A3, A2, A1, A0};
|
||||
wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
|
||||
reg [15:0] mem = INIT;
|
||||
assign SPO = mem[a];
|
||||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(negedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1153 *)
|
||||
|
|
@ -494,6 +961,29 @@ module RAM32X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM32X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire [4:0] a = {A4, A3, A2, A1, A0};
|
||||
wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
|
||||
reg [31:0] mem = INIT;
|
||||
assign SPO = mem[a];
|
||||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(negedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1153 *)
|
||||
|
|
@ -517,6 +1007,29 @@ module RAM64X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM64X1D_1 (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
|
||||
wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
|
||||
reg [63:0] mem = INIT;
|
||||
assign SPO = mem[a];
|
||||
assign DPO = mem[dpra];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(negedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc9_arrival=1153 *)
|
||||
|
|
@ -537,6 +1050,290 @@ module RAM128X1D (
|
|||
always @(posedge clk) if (WE) mem[A] <= D;
|
||||
endmodule
|
||||
|
||||
module RAM256X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input [7:0] A, DPRA
|
||||
);
|
||||
parameter INIT = 256'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
reg [255:0] mem = INIT;
|
||||
assign SPO = mem[A];
|
||||
assign DPO = mem[DPRA];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk) if (WE) mem[A] <= D;
|
||||
endmodule
|
||||
|
||||
// Multi port.
|
||||
|
||||
module RAM32M (
|
||||
output [1:0] DOA,
|
||||
output [1:0] DOB,
|
||||
output [1:0] DOC,
|
||||
output [1:0] DOD,
|
||||
input [4:0] ADDRA,
|
||||
input [4:0] ADDRB,
|
||||
input [4:0] ADDRC,
|
||||
input [4:0] ADDRD,
|
||||
input [1:0] DIA,
|
||||
input [1:0] DIB,
|
||||
input [1:0] DIC,
|
||||
input [1:0] DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
reg [63:0] mem_a = INIT_A;
|
||||
reg [63:0] mem_b = INIT_B;
|
||||
reg [63:0] mem_c = INIT_C;
|
||||
reg [63:0] mem_d = INIT_D;
|
||||
assign DOA = mem_a[2*ADDRA+:2];
|
||||
assign DOB = mem_b[2*ADDRB+:2];
|
||||
assign DOC = mem_c[2*ADDRC+:2];
|
||||
assign DOD = mem_d[2*ADDRD+:2];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk)
|
||||
if (WE) begin
|
||||
mem_a[2*ADDRD+:2] <= DIA;
|
||||
mem_b[2*ADDRD+:2] <= DIB;
|
||||
mem_c[2*ADDRD+:2] <= DIC;
|
||||
mem_d[2*ADDRD+:2] <= DID;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RAM32M16 (
|
||||
output [1:0] DOA,
|
||||
output [1:0] DOB,
|
||||
output [1:0] DOC,
|
||||
output [1:0] DOD,
|
||||
output [1:0] DOE,
|
||||
output [1:0] DOF,
|
||||
output [1:0] DOG,
|
||||
output [1:0] DOH,
|
||||
input [4:0] ADDRA,
|
||||
input [4:0] ADDRB,
|
||||
input [4:0] ADDRC,
|
||||
input [4:0] ADDRD,
|
||||
input [4:0] ADDRE,
|
||||
input [4:0] ADDRF,
|
||||
input [4:0] ADDRG,
|
||||
input [4:0] ADDRH,
|
||||
input [1:0] DIA,
|
||||
input [1:0] DIB,
|
||||
input [1:0] DIC,
|
||||
input [1:0] DID,
|
||||
input [1:0] DIE,
|
||||
input [1:0] DIF,
|
||||
input [1:0] DIG,
|
||||
input [1:0] DIH,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_E = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_F = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_G = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_H = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
reg [63:0] mem_a = INIT_A;
|
||||
reg [63:0] mem_b = INIT_B;
|
||||
reg [63:0] mem_c = INIT_C;
|
||||
reg [63:0] mem_d = INIT_D;
|
||||
reg [63:0] mem_e = INIT_E;
|
||||
reg [63:0] mem_f = INIT_F;
|
||||
reg [63:0] mem_g = INIT_G;
|
||||
reg [63:0] mem_h = INIT_H;
|
||||
assign DOA = mem_a[2*ADDRA+:2];
|
||||
assign DOB = mem_b[2*ADDRB+:2];
|
||||
assign DOC = mem_c[2*ADDRC+:2];
|
||||
assign DOD = mem_d[2*ADDRD+:2];
|
||||
assign DOE = mem_e[2*ADDRE+:2];
|
||||
assign DOF = mem_f[2*ADDRF+:2];
|
||||
assign DOG = mem_g[2*ADDRG+:2];
|
||||
assign DOH = mem_h[2*ADDRH+:2];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk)
|
||||
if (WE) begin
|
||||
mem_a[2*ADDRH+:2] <= DIA;
|
||||
mem_b[2*ADDRH+:2] <= DIB;
|
||||
mem_c[2*ADDRH+:2] <= DIC;
|
||||
mem_d[2*ADDRH+:2] <= DID;
|
||||
mem_e[2*ADDRH+:2] <= DIE;
|
||||
mem_f[2*ADDRH+:2] <= DIF;
|
||||
mem_g[2*ADDRH+:2] <= DIG;
|
||||
mem_h[2*ADDRH+:2] <= DIH;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RAM64M (
|
||||
output DOA,
|
||||
output DOB,
|
||||
output DOC,
|
||||
output DOD,
|
||||
input [4:0] ADDRA,
|
||||
input [4:0] ADDRB,
|
||||
input [4:0] ADDRC,
|
||||
input [4:0] ADDRD,
|
||||
input DIA,
|
||||
input DIB,
|
||||
input DIC,
|
||||
input DID,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
reg [63:0] mem_a = INIT_A;
|
||||
reg [63:0] mem_b = INIT_B;
|
||||
reg [63:0] mem_c = INIT_C;
|
||||
reg [63:0] mem_d = INIT_D;
|
||||
assign DOA = mem_a[ADDRA];
|
||||
assign DOB = mem_b[ADDRB];
|
||||
assign DOC = mem_c[ADDRC];
|
||||
assign DOD = mem_d[ADDRD];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk)
|
||||
if (WE) begin
|
||||
mem_a[ADDRD] <= DIA;
|
||||
mem_b[ADDRD] <= DIB;
|
||||
mem_c[ADDRD] <= DIC;
|
||||
mem_d[ADDRD] <= DID;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RAM64M8 (
|
||||
output DOA,
|
||||
output DOB,
|
||||
output DOC,
|
||||
output DOD,
|
||||
output DOE,
|
||||
output DOF,
|
||||
output DOG,
|
||||
output DOH,
|
||||
input [4:0] ADDRA,
|
||||
input [4:0] ADDRB,
|
||||
input [4:0] ADDRC,
|
||||
input [4:0] ADDRD,
|
||||
input [4:0] ADDRE,
|
||||
input [4:0] ADDRF,
|
||||
input [4:0] ADDRG,
|
||||
input [4:0] ADDRH,
|
||||
input DIA,
|
||||
input DIB,
|
||||
input DIC,
|
||||
input DID,
|
||||
input DIE,
|
||||
input DIF,
|
||||
input DIG,
|
||||
input DIH,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE
|
||||
);
|
||||
parameter [63:0] INIT_A = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_B = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_C = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_D = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_E = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_F = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_G = 64'h0000000000000000;
|
||||
parameter [63:0] INIT_H = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
reg [63:0] mem_a = INIT_A;
|
||||
reg [63:0] mem_b = INIT_B;
|
||||
reg [63:0] mem_c = INIT_C;
|
||||
reg [63:0] mem_d = INIT_D;
|
||||
reg [63:0] mem_e = INIT_E;
|
||||
reg [63:0] mem_f = INIT_F;
|
||||
reg [63:0] mem_g = INIT_G;
|
||||
reg [63:0] mem_h = INIT_H;
|
||||
assign DOA = mem_a[ADDRA];
|
||||
assign DOB = mem_b[ADDRB];
|
||||
assign DOC = mem_c[ADDRC];
|
||||
assign DOD = mem_d[ADDRD];
|
||||
assign DOE = mem_e[ADDRE];
|
||||
assign DOF = mem_f[ADDRF];
|
||||
assign DOG = mem_g[ADDRG];
|
||||
assign DOH = mem_h[ADDRH];
|
||||
wire clk = WCLK ^ IS_WCLK_INVERTED;
|
||||
always @(posedge clk)
|
||||
if (WE) begin
|
||||
mem_a[ADDRH] <= DIA;
|
||||
mem_b[ADDRH] <= DIB;
|
||||
mem_c[ADDRH] <= DIC;
|
||||
mem_d[ADDRH] <= DID;
|
||||
mem_e[ADDRH] <= DIE;
|
||||
mem_f[ADDRH] <= DIF;
|
||||
mem_g[ADDRH] <= DIG;
|
||||
mem_h[ADDRH] <= DIH;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// ROM.
|
||||
|
||||
module ROM16X1 (
|
||||
output O,
|
||||
input A0, A1, A2, A3
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0;
|
||||
assign O = INIT[{A3, A2, A1, A0}];
|
||||
endmodule
|
||||
|
||||
module ROM32X1 (
|
||||
output O,
|
||||
input A0, A1, A2, A3, A4
|
||||
);
|
||||
parameter [31:0] INIT = 32'h0;
|
||||
assign O = INIT[{A4, A3, A2, A1, A0}];
|
||||
endmodule
|
||||
|
||||
module ROM64X1 (
|
||||
output O,
|
||||
input A0, A1, A2, A3, A4, A5
|
||||
);
|
||||
parameter [63:0] INIT = 64'h0;
|
||||
assign O = INIT[{A5, A4, A3, A2, A1, A0}];
|
||||
endmodule
|
||||
|
||||
module ROM128X1 (
|
||||
output O,
|
||||
input A0, A1, A2, A3, A4, A5, A6
|
||||
);
|
||||
parameter [127:0] INIT = 128'h0;
|
||||
assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}];
|
||||
endmodule
|
||||
|
||||
module ROM256X1 (
|
||||
output O,
|
||||
input A0, A1, A2, A3, A4, A5, A6, A7
|
||||
);
|
||||
parameter [255:0] INIT = 256'h0;
|
||||
assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}];
|
||||
endmodule
|
||||
|
||||
// Shift registers.
|
||||
|
||||
module SRL16E (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc9_arrival=1472 *)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue