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Update Changelog

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Miodrag Milanovic 2022-09-06 08:22:23 +02:00
parent 6d5adb6a65
commit 0ff129c10b
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CHANGELOG
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@ -11,6 +11,7 @@ Yosys 0.20 .. Yosys 0.20-dev
present in yosys witness traces present in yosys witness traces
- Added option "-hdlname" to "sim" pass - preserves hiearachy when writing - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
simulation output for a flattened design simulation output for a flattened design
- Addded option "-scramble-name" to "rename" pass
* Formal Verification * Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained - Added $anyinit cell to directly represent FFs with an unconstrained
@ -23,6 +24,18 @@ Yosys 0.20 .. Yosys 0.20-dev
conversion. conversion.
- yosys-witness: Conversion from and to AIGER witness traces. - yosys-witness: Conversion from and to AIGER witness traces.
* Verific support
- Filename re-writing support for "verific" pass.
* Various
- ABC performance improvements
- Filename re-writing added for "show -lib".
* SmartFusion2 support
- Added $alu support
- Added SYSRESET and XTLOSC cells
- Compatible now with LiberoSoc flow
Yosys 0.19 .. Yosys 0.20 Yosys 0.19 .. Yosys 0.20
-------------------------- --------------------------
* New commands and options * New commands and options