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Add support for optimizing exists-forall problems.

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Modifies smt2 backend to recognize `$anyconst` etc. assigned to a wire with the `maximize` or `minimize` attribute and emit `; yosys-smt2-maximize` or `; yosys-smt2-minimize` directives as appropriate.
Modifies `backends/smt2/smtbmc.py` and `smtio.py` to recognize those directives and emit a `(maximize ...)` or `(minimize ...)` command at the end of `smt_forall_assert()`, as described in the paper "νZ - An Optimizing SMT Solver" by Nikolaj Bjørner et al.
Adds an example `examples/smtbmc/demo9.v` to show how it can be used.
This commit is contained in:
Alberto Gonzalez 2020-03-08 06:34:47 +00:00
parent bfeba9ad11
commit 0fda8308bc
5 changed files with 55 additions and 3 deletions
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11
examples/smtbmc/Makefile
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@ -1,5 +1,5 @@
all: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8
all: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9
demo1: demo1.smt2
yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
@ -28,6 +28,9 @@ demo7: demo7.smt2
demo8: demo8.smt2
yosys-smtbmc -s z3 -t 1 -g demo8.smt2
demo9: demo9.smt2
yosys-smtbmc -s z3 -t 1 -g demo9.smt2
demo1.smt2: demo1.v
yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires demo1.smt2'
@ -52,6 +55,9 @@ demo7.smt2: demo7.v
demo8.smt2: demo8.v
yosys -ql demo8.yslog -p 'read_verilog -formal demo8.v; prep -top demo8 -nordff; write_smt2 -stbv -wires demo8.smt2'
demo9.smt2: demo9.v
yosys -ql demo9.yslog -p 'read_verilog -formal demo9.v; prep -top demo9 -nordff; write_smt2 -stbv -wires demo9.smt2'
clean:
rm -f demo1.yslog demo1.smt2 demo1.vcd
rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
@ -61,6 +67,7 @@ clean:
rm -f demo6.yslog demo6.smt2
rm -f demo7.yslog demo7.smt2
rm -f demo8.yslog demo8.smt2
rm -f demo9.yslog demo9.smt2
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 clean
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean

13
examples/smtbmc/demo9.v Normal file
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@ -0,0 +1,13 @@
module demo9;
(* maximize *) wire[7:0] h = $anyconst;
wire [7:0] i = $allconst;
wire [7:0] t0 = ((i << 8'b00000010) + 8'b00000011);
wire trigger = (t0 > h) && (h < 8'b00000100);
always @* begin
assume(trigger == 1'b1);
cover(1);
end
endmodule