mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-06 19:21:23 +00:00
Merge 7047bc26b3
into 366cb5e6dd
This commit is contained in:
commit
0fd0a9056d
27 changed files with 3694 additions and 3566 deletions
|
@ -1334,7 +1334,7 @@ struct RTLIL::Design
|
|||
dict<RTLIL::IdString, RTLIL::Module*> modules_;
|
||||
std::vector<RTLIL::Binding*> bindings_;
|
||||
|
||||
std::vector<AST::AstNode*> verilog_packages, verilog_globals;
|
||||
std::vector<std::unique_ptr<AST::AstNode>> verilog_packages, verilog_globals;
|
||||
std::unique_ptr<define_map_t> verilog_defines;
|
||||
|
||||
std::vector<RTLIL::Selection> selection_stack;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue