mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-04 10:20:24 +00:00
Code Activity

Merge 7047bc26b3 into 366cb5e6dd

Browse source
This commit is contained in:
Emil J 2025-08-02 14:04:21 +12:00 • committed by GitHub
commit 0fd0a9056d
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
27 changed files with 3694 additions and 3566 deletions
Download patch file Download diff file Expand all files Collapse all files

17
kernel/rtlil.cc
View file

@ -952,10 +952,6 @@ RTLIL::Design::~Design()
delete pr.second;
for (auto n : bindings_)
delete n;
for (auto n : verilog_packages)
delete n;
for (auto n : verilog_globals)
delete n;
#ifdef WITH_PYTHON
RTLIL::Design::get_all_designs()->erase(hashidx_);
#endif
@ -5710,16 +5706,10 @@ static void sigspec_parse_split(std::vector<std::string> &tokens, const std::str
tokens.push_back(text.substr(start));
}
static int sigspec_parse_get_dummy_line_num()
{
return 0;
}
bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
{
cover("kernel.rtlil.sigspec.parse");
AST::current_filename = "input";
std::vector<std::string> tokens;
sigspec_parse_split(tokens, str, ',');
@ -5735,12 +5725,11 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
cover("kernel.rtlil.sigspec.parse.const");
AST::get_line_num = sigspec_parse_get_dummy_line_num;
AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
if (ast == NULL)
VERILOG_FRONTEND::ConstParser p{location()};
auto ast = p.const2ast(netname);
if (ast == nullptr)
return false;
sig.append(RTLIL::Const(ast->bits));
delete ast;
continue;
}