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Merge pull request #5158 from georgerennie/george/task_inout

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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
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George Rennie 2025-06-04 14:23:08 +01:00 • committed by GitHub
commit 0fcf5c080d
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2 changed files with 146 additions and 6 deletions
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20
frontends/ast/simplify.cc
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@ -4100,16 +4100,24 @@ skip_dynamic_range_lvalue_expansion:;
delete arg;
continue;
}
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
wire_id->str = wire->str;
AstNode *assign = child->is_input ?
new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
new AstNode(AST_ASSIGN_EQ, arg, wire_id);
assign->children[0]->was_checked = true;
if (child->is_input)
if (child->is_input) {
AstNode *assign = new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
assign->children[0]->was_checked = true;
new_stmts.push_back(assign);
else
}
if (child->is_output) {
AstNode *assign = new AstNode(AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
assign->children[0]->was_checked = true;
output_assignments.push_back(assign);
}
delete arg;
delete wire_id;
}
}