diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 749767743..3d33f9de0 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -4100,16 +4100,24 @@ skip_dynamic_range_lvalue_expansion:;
 						delete arg;
 						continue;
 					}
+
 					AstNode *wire_id = new AstNode(AST_IDENTIFIER);
 					wire_id->str = wire->str;
-					AstNode *assign = child->is_input ?
-							new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
-							new AstNode(AST_ASSIGN_EQ, arg, wire_id);
-					assign->children[0]->was_checked = true;
-					if (child->is_input)
+
+					if (child->is_input) {
+						AstNode *assign = new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
+						assign->children[0]->was_checked = true;
 						new_stmts.push_back(assign);
-					else
+					}
+
+					if (child->is_output) {
+						AstNode *assign = new AstNode(AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
+						assign->children[0]->was_checked = true;
 						output_assignments.push_back(assign);
+					}
+
+					delete arg;
+					delete wire_id;
 				}
 			}
 
diff --git a/tests/verilog/func_task_arg_copying.ys b/tests/verilog/func_task_arg_copying.ys
new file mode 100644
index 000000000..e87c2781b
--- /dev/null
+++ b/tests/verilog/func_task_arg_copying.ys
@@ -0,0 +1,132 @@
+# https://github.com/YosysHQ/yosys/issues/5157
+read_verilog -sv <<EOT
+module stmt_if_task (
+    output logic [7:0] out_val_m6,
+    input logic [7:0] in_val_m6,
+    input bit condition_m6
+);
+    logic [7:0] var_m6;
+    task automatic update_conditional_m6(input bit cond, inout logic [7:0] val);
+        if (cond) begin
+            val++;
+        end else begin
+            --val;
+        end
+    endtask
+    always_comb begin
+        var_m6 = in_val_m6;
+        update_conditional_m6(condition_m6, var_m6);
+        out_val_m6 = var_m6;
+    end
+
+    wire [7:0] m6_inc = in_val_m6 + 1;
+    wire [7:0] m6_dec = in_val_m6 - 1;
+    always_comb assert(out_val_m6 == (condition_m6 ? m6_inc : m6_dec));
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify
+
+design -reset
+
+read_verilog -sv <<EOT
+module top (
+	output logic [7:0] out
+);
+	task automatic set_to_5(inout logic [7:0] val);
+		val = 5;
+	endtask
+
+	always_comb begin
+		out = 0;
+		set_to_5(out);
+	end
+
+	always_comb assert(out == 5);
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify
+
+design -reset
+
+read_verilog -sv <<EOT
+module top (
+	output logic [7:0] a,
+	output logic [7:0] b,
+	output logic [7:0] c
+);
+	task automatic modify(
+		input logic [7:0] t_in,
+		output logic [7:0] t_out,
+		inout logic [7:0] t_inout
+	);
+		assert(t_in == 5);
+		t_in = 6;
+		t_out = 7;
+		assert(t_inout == 8);
+		t_inout = 9;
+	endtask
+
+	always_comb begin
+		a = 5;
+		b = 4;
+		c = 8;
+
+		modify(a, b, c);
+
+		assert(a == 5);
+		assert(b == 7);
+		assert(c == 9);
+	end
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify
+
+design -reset
+
+read_verilog -sv <<EOT
+module top (
+	output logic [7:0] a,
+	output logic [7:0] b,
+	output logic [7:0] c
+);
+	function logic [7:0] modify(
+		input logic [7:0] t_in,
+		output logic [7:0] t_out,
+		inout logic [7:0] t_inout
+	);
+		assert(t_in == 5);
+		t_in = 6;
+		t_out = 7;
+		assert(t_inout == 8);
+		t_inout = 9;
+		modify = 10;
+	endfunction
+
+	logic [7:0] result;
+	always_comb begin
+		a = 5;
+		b = 4;
+		c = 8;
+
+		result = modify(a, b, c);
+
+		assert(a == 5);
+		assert(b == 7);
+		assert(c == 9);
+		assert(result == 10);
+	end
+endmodule
+EOT
+
+prep
+chformal -lower
+sat -prove-asserts -verify