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https://github.com/YosysHQ/yosys
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Merge 5be4727740
into 733487e730
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commit
0fc7ce3022
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@ -48,7 +48,7 @@ struct OptLutWorker
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int eliminated_count = 0, combined_count = 0;
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bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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State evaluate_lut_x(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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SigSpec lut_input = sigmap(lut->getPort(ID::A));
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int lut_width = lut->getParam(ID::WIDTH).as_int();
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@ -68,7 +68,12 @@ struct OptLutWorker
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}
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}
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return lut_table.extract(lut_index).as_bool();
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return lut_table.bits[lut_index];
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}
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bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
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{
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return evaluate_lut_x(lut, inputs) != State::S0;
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}
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void show_stats_by_arity()
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@ -520,6 +525,46 @@ struct OptLutWorker
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}
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}
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show_stats_by_arity();
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if (!dlogic.empty()) {
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// We don't have handling for the constraints, so until then, disable
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// narrowing.
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log("Narrowing LUTs skipped: constraints in place.\n");
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return;
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}
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log("\n");
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log("Narrowing LUTs.\n");
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worklist = luts;
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while (worklist.size())
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{
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auto lut = worklist.pop();
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SigSpec lut_input = sigmap(lut->getPort(ID::A));
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SigSpec lut_new_input = lut_input;
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lut_new_input.remove_const();
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if (lut_new_input.size() == lut_input.size())
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continue;
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log_debug("Found to-be-narrowed cell %s.%s.\n", log_id(module), log_id(lut));
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int lut_width = lut_new_input.size();
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RTLIL::Const lut_new_table(State::Sx, 1 << lut_width);
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for (int eval = 0; eval < 1 << lut_width; eval++)
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{
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dict<SigBit, bool> eval_inputs;
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eval_inputs[State::S0] = false;
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eval_inputs[State::S1] = true;
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for (size_t i = 0; i < (size_t) lut_new_input.size(); i++)
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eval_inputs[lut_new_input[i]] = (eval >> i) & 1;
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lut_new_table.bits[eval] = evaluate_lut_x(lut, eval_inputs);
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}
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lut->setPort(ID::A, lut_new_input);
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lut->setParam(ID::WIDTH, lut_width);
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lut->setParam(ID::LUT, lut_new_table);
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}
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}
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};
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