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Progress in presentation

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Clifford Wolf 2014-02-17 09:45:04 +01:00
parent ca53ef5098
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manual/PRESENTATION_Intro.tex
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@ -326,7 +326,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
Read Verilog source file and convert to internal representation.
}%
\only<2>{
Elaborate the design hierarchy. Should alsways be the first
Elaborate the design hierarchy. Should always be the first
command after reading the design.
}%
\only<3>{
@ -794,7 +794,7 @@ We need you as a developer:
\begin{frame}{\subsecname}
\begin{itemize}
\item Yosys is a powerful tool and framework for Verilog synthesis.
\item Is uses a command-based interface and can be controlled by scripts.
\item It uses a command-based interface and can be controlled by scripts.
\item By combining existing commands and implementing new commands Yosys can
be used in a wide range of application far beyond simple synthesis.
\end{itemize}