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docs: more tidying
Fix 010 pdf link. Swap yosys script code blocks for literal includes. Fix broken example code.
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========
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This document was originally published in April 2015:
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:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
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:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_010_Verilog_to_BLIF.pdf>`
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..
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Installation
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