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Move global ABC configuration variables into AbcConfig and initialize them properly

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This commit is contained in:
Robert O'Callahan 2025-11-03 15:45:30 +00:00
parent d0a41d4f58
commit 0f770285f3
2 changed files with 80 additions and 56 deletions
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tests/techmap/abc_state.ys Normal file
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read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
abc -g all
design -reset
read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
techmap
abc -g AND
select -assert-count 0 t:$_OR_
select -assert-count 1 t:$_AND_