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sf2: add a test for $alu gate

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Tristan Gingold 2021-11-24 17:09:59 +01:00
parent c25f3ff3df
commit 0f6cf8b8e4
1 changed files with 22 additions and 0 deletions
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techlibs/sf2/tests/test_arith.ys Normal file
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# Our implementation
read_verilog ../arith_map.v
read_verilog ../cells_sim.v
read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
rename \$__SF2_ALU gate
hierarchy -top gate -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
flatten
opt
write_verilog gate.v
# The reference
read_verilog -DSIMLIB_NOCHECKS ../../common/simlib.v
rename \$alu gold
hierarchy -top gold -chparam A_WIDTH 4 -chparam B_WIDTH 5 -chparam Y_WIDTH 5
flatten
proc
clean
write_verilog gold.v
read_verilog gate.v
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter