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add additional dff and lutram tests

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Miodrag Milanovic 2023-04-04 11:18:24 +02:00 committed by myrtle
parent 54d313efc3
commit 0f5e7c244d
2 changed files with 57 additions and 0 deletions
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40
tests/arch/machxo2/adffs.ys Normal file
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read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:TRELLIS_FF
select -assert-count 1 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D

17
tests/arch/machxo2/lutram.ys Normal file
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read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 20 t:LUT4
select -assert-count 8 t:TRELLIS_DPR16X4
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D